Analog to digital converters have increased in speed and bit depth over the years to satisfy commercial and defense requirements for SFDR, SNR, Bandwidth, and ENOB. Quantization errors, timing errors, and nonlinearities still prevent ADCs from satisfying some system application requirements. Several types of compensation have been developed to address errors among other things dithering, calibration, and commutating ADCs at lower rates with modest improvements to spurious-free dynamic range (SFDR).
Our group is introducing a novel spur removal technique that has demonstrated consistent improvement of SFDR by 9dB and more in our lab. This process is ADC-type, clock-frequency, and CW frequency agnostic, requires no calibration or learning time period, and minimizes the amount of post-processing or errant signal analysis in the end-user application. Further, the processing required for spur removal may be executed in either a low latency mode for EW or in a real-time mode for ISR, radar, or communication.
The approach, called HDRR, employs non-uniform sampling and an advanced clocking and sampling approach that mitigates the spurs and the resulting intermodulation distortion. It also preserves the original phase and amplitude of the signal as measured at the antenna. Non-uniform sampling allows a receiver system to determine the signal’s Nyquist zone location and equips the receiver to extract additional information from it.